Virtual Machine Instructions

 

Overview

The DRM virtual machine is a register machine architecture similar to most modern Von Neumann computer architectures. Because the DRM virtual machine is expected to service a database, the virtual machine memory has been subdivided into dynamically typed words. Hence the name, Dynamic typed Register Machine. With the machine memory subdivided into dynamically typed words, data (from the database) with a wide variety of types, can be easily loaded into memory; and, since the register machine architecture is similar to the internal architecture of most modern computing equipment, it is easy to write just-in-time compilers from DRM pcodes into native binary machine code for a wide variety of computers.

The Analytic Information Server virtual machine architecture is composed of the following components:

The DRM virtual machine supports a number of registers, including an Instruction Pointer register, a Stack Register, and fifty general purpose Arithmetic Registers. Each general purpose arithmetic register can store Integer, IEEE floating point, or memory address data. Virtual machine instructions can operate directly on the contents of registers or on memory locations pointed to by addresses in registers. Memory references can be made: (a) directly from addresses in registers; (b) indirectly from addresses in registers indexed by integers in an index register; or (c) indirectly from addresses in registers plus an inline integer displacement. The virtual machine instructions operate on the following data types:

Word Format

The AIS Word is a 128-bit dynamically typed container capable of holding any of the AIS native data types (shown above). Each Word begins with an 80-bit data area capable of holding up to ten bytes of null-terminated ASCII text, or any one of these other native AIS data types: Character, Boolean, Float, Integer, Number, Object, or Short. Immediately following the Word's 80-bit data area, is the Word's tail (a 32-bit signed integer). The tail is a general purpose data field used for linking words to other words, keeping word counts, or any other purpose. Immediately following the Word's tail, is the Word's Declared Type (an 8-bit data type announcing the user's preferred data type for this Word). Immediately following the Word's Declared Type, is the Word's Current Type (an 8-bit data type announcing the type of data contained in the Word's 80-bit data area).

Assembler

For each virtual machine instruction there is a Lisp special form which generates the specified vm instruction. This allows Lisp to perform double duty as a vm assembler language. As the Analytic Information Server (AIS) virtual machine is ported from machine to machine, AIS Lisp becomes a write-once-run-anywhere assembler language.

Virtual Machine Instructions

AIS Lambdas are designed to be write-once-run-anywhere executable objects. This is accomplished via the virtual machine concept of software Lambda execution. Lambda virtual machines are designed to be mapped onto the actual host microchip at the server location, providing faithful Lambda execution wherever the Lambda may travel on the Internet. There are currently several virtual machines operating within Analytic Information Server. The DRM virtual machine uses a Dynamically typed Register Machine model to provide portable Lambda execution from high level dynamically typed instructions all the way to super fast microchip-level register execution. The DRM virtual machine runs in emulation mode during the testing and debug phases of Lambda development, and there is an AIS Lambda debugger available for Lambdas running on this virtual machine. During the final release phases of Lambda development, DRM virtual machine Lambdas are automatically converted to the NATIVE virtual machine on the host computer, using the just-in-time compiler. The NATIVE virtual machine is a faithful machine language translation of the execution rules in the DRM virtual machine onto the actual host microchip at the server location. NATIVE virtual machine execution runs at microchip-level execution speeds.

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vmimulvmiorvmiorbvmisubvmixor
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vmnatAddIntegervmnatAddNumbervmnatAndIntegervmnatDivIntegervmnatDivNumber
vmnatDivrIntegervmnatDivrNumbervmnatJumpCCIntegervmnatJumpCCNumbervmnatLoadCharacter
vmnatLoadFloatvmnatLoadIntegervmnatLoadLongvmnatLoadNumbervmnatLoadObject
vmnatLoadShortvmnatMulIntegervmnatMulNumbervmnatOrIntegervmnatSaveCharacter
vmnatSaveFloatvmnatSaveIntegervmnatSaveLongvmnatSaveNumbervmnatSaveObject
vmnatSaveShortvmnatShlIntegervmnatShrIntegervmnatSubIntegervmnatSubNumber
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vmnsubvmonerrorvmoptvmorvmpop
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vmregLoadIntegervmregLoadJmpPointervmregLoadNumbervmregLoadTailvmregLoadType
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vmregMulImmediatevmregMulIntegervmregMulNumbervmregNumbervmregObjLength
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vmregSaveDeclTypeImmediatevmregSaveIntegervmregSaveNumbervmregSaveTailvmregSaveTailImmediate
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vmregSetLongvmregSetLongImmediatevmregSetNumbervmregSetShortvmregSetShortImmediate
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vmregSubImmediatevmregSubIntegervmregSubNumbervmregSubPointervmregTanNumber
vmregXorImmediatevmregXorIntegervmreturnvmselfvmsend
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vmsetmatrixvmsetnummatrixvmsetnumvectorvmsetobjvectorvmsetpcdvector
vmsetshortvectorvmsetstringvmsetstrkeyvmsetstrvaluevmsetvector
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