Lisp Assembler

 

Introduction

The Lisp language is designed to be used as an assembler language for the DRM virtual machine. For each virtual machine instruction there is a Lisp builtin form. These vm forms cannot be executed directly. They can only be executed within the context of a compiled Lambda object. All Lisp assembler special forms are prefixed with the vm letters, and are understood only by the Lisp compiler.

The Lambda Information Server database engine comes with a built in virtual machine (DRM) for managing distributed intelligent Lambda execution. Analytic Information Server also supports multiple virtual machines (as many as one per Lambda), and execution of Lambdas on native binary machine code.

The DRM virtual machine instruction set, which is machine independent and computationally complete, is designed for fast execution. The design goal is to come as close as possible to compiled C execution speeds, while still retaining portability. The Analytic Information Server engine does not force the user to choose an Lambda source language syntax, instead compilers are supplied for Lisp, JavaScript, and even natural language.

The Lambda Information Server engine performs its own state of the art object management for all Lambda objects supervised by the database engine. Lambda Information Server manages all of its own object tables to maximize execution speed.  The Lambda Information Server engine supports: fully automated mark and sweep garbage collection; a user extendible type system; dynamic object creation; optimized object messaging; both object and Lambda inheritance; mixed or interleaved execution of intelligent Lambdas and host functions, line by line source code debugging of Lambdas, and full object, Lambda, and code level browsing.

Multiple Virtual Machines

AIS Lambdas are designed to be write-once-run-anywhere executable objects. This is accomplished via the virtual machine concept of software Lambda execution. Lambda virtual machines are designed to be mapped onto the actual host microchip at the server location, providing faithful Lambda execution wherever the Lambda may travel on the Internet. There are currently several virtual machines operating within Analytic Information Server. The DRM virtual machine uses a Dynamically typed Register Machine model to provide portable Lambda execution from high level dynamically typed instructions all the way to super fast microchip-level register execution. The DRM virtual machine runs in emulation mode during the testing and debug phases of Lambda development, and there is an AIS Lambda debugger available for Lambdas running on this virtual machine. During the final release phases of Lambda development, DRM virtual machine Lambdas are automatically converted to the NATIVE virtual machine on the host computer, using the just-in-time compiler. The NATIVE virtual machine is a faithful machine language translation of the execution rules in the DRM virtual machine onto the actual host microchip at the server location. NATIVE virtual machine execution runs at microchip-level execution speeds.

Analytic Information Server is agnostic in the choice of Lambda virtual machine. It is certainly possible, and is currently often the practice to have communities of Lambdas which are not all running on the same virtual machine. It is often the case that one virtual machine model is preferable for certain data analysis applications while yet another virtual machine model is preferable for other data analysis applications. AIS comes equipped with several Lambda virtual machines and loadable library tools for the easy creation of additional user-defined Lambda virtual machines. The only caveat is that popular virtual machines (such as the Python, Java, or Smalltalk virtual machines) implemented in Analytic Information Server must be tailored to execute our executable Lambda objects, and to operate within the AIS runtime environment. AIS virtual machine development tools are not designed to create virtual machines for execution outside Lambda Information Server.

Microchip-level Execution Speeds

Analytic Information Server is primarily concerned with software Lambdas which perform high volume data analysis. Super fast execution speed is essential in such application domains. There are several levels of general computer program execution speeds. Disk based operations, such as those performed by SQL and other database system languages, are among the slowest executing animals in the program zoo. The next level of faster execution speed is achieved by programs performing memory to memory operations, such as those performed by COBOL and many other business languages. The fastest possible level of program execution is achieved by programs performing register to register operations on the microchip, such as those performed by assembler language.

The AIS DRM virtual machine provides very fast native execution of Lambdas performing disk based operations, memory to memory operations, and microchip-level register to register operations. Regardless of the data analysis domain, AIS allows the development of write-once-run-anywhere Lambdas which execute at the fastest possible speeds.

 

Architecture

The DRM virtual machine is a register machine architecture similar to most modern Von Neumann computer architectures. Because the DRM virtual machine is expected to service a database, the virtual machine memory has been subdivided into dynamically typed words. Hence the name, Dynamic typed Register Machine. With the machine memory subdivided into dynamically typed words, data (from the database) with a wide variety of types, can be easily loaded into memory; and, since the register machine architecture is similar to the internal architecture of most modern computing equipment, it is easy to write just-in-time compilers from DRM pcodes into native binary machine code for a wide variety of computers.

The DRM virtual machine supports a number of registers, including an Instruction Pointer register, a Stack Register, and fifty general purpose Arithmetic Registers. Each general purpose arithmetic register can store Integer, IEEE floating point, or memory address data. Virtual machine instructions can operate directly on the contents of registers or on memory locations pointed to by addresses in registers. Memory references can be made: (a) directly from addresses in registers; (b) indirectly from addresses in registers indexed by integers in an index register; or (c) indirectly from addresses in registers plus an inline integer displacement. The virtual machine instructions operate on the following data types:

Word Format

The AIS Word is a 128-bit dynamically typed container capable of holding any of the AIS native data types (shown above). Each Word begins with an 80-bit data area capable of holding up to ten bytes of null-terminated ASCII text, or any one of these other native AIS data types: Character, Boolean, Float, Integer, Long, Number, Object, or Short. Immediately following the Word's 80-bit data area, is the Word's tail (a 32-bit signed integer). The tail is a general purpose data field used for linking words to other words, keeping word counts, or any other purpose. Immediately following the Word's tail, is the Word's Declared Type (an 8-bit data type announcing the user's preferred data type for this Word). Immediately following the Word's Declared Type, is the Word's Current Type (an 8-bit data type announcing the type of data contained in the Word's 80-bit data area). The format of each AIS Word is as follows.

Assembler

For each virtual machine instruction there is a Lisp special form which generates the specified vm instruction. This allows Lisp to perform double duty as a vm assembler language. As the Analytic Information Server (AIS) virtual machine is ported from machine to machine, AIS Lisp becomes a write-once-run-anywhere assembler language.

Virtual Machine Instructions

AIS Lambdas are designed to be write-once-run-anywhere executable objects. This is accomplished via the virtual machine concept of software Lambda execution. Lambda virtual machines are designed to be mapped onto the actual host microchip at the server location, providing faithful Lambda execution wherever the Lambda may travel on the Internet. There are currently several virtual machines operating within Analytic Information Server. The DRM virtual machine uses a Dynamically typed Register Machine model to provide portable Lambda execution from high level dynamically typed instructions all the way to super fast microchip-level register execution. The DRM virtual machine runs in emulation mode during the testing and debug phases of Lambda development, and there is an AIS Lambda debugger available for Lambdas running on this virtual machine. During the final release phases of Lambda development, DRM virtual machine Lambdas are automatically converted to the NATIVE virtual machine on the host computer, using the just-in-time compiler. The NATIVE virtual machine is a faithful machine language translation of the execution rules in the DRM virtual machine onto the actual host microchip at the server location. NATIVE virtual machine execution runs at microchip-level execution speeds.

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vmnatLoadShortvmnatMulIntegervmnatMulNumbervmnatOrIntegervmnatSaveCharacter
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vmnatSaveShortvmnatShlIntegervmnatShrIntegervmnatSubIntegervmnatSubNumber
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vmpushvmrefvmrefbitvectorvmrefbytevectorvmrefdickey
vmrefdicvaluevmrefdirkeyvmrefdirvaluevmreffltvectorvmrefintvector
vmreflongvectorvmrefmatrixvmrefnummatrixvmrefnumvectorvmrefobjvector
vmrefpcdvectorvmrefshortvectorvmrefstringvmrefstrkeyvmrefstrvalue
vmrefsymbolvmreftextvmrefvectorvmregAbsNumbervmregAddImmediate
vmregAddIntegervmregAddNumbervmregAddPointervmregAndImmediatevmregAndInteger
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vmregDivrIntegervmregDivrNumbervmregIncPointervmregIntegervmregJump
vmregJumpCCImmediatevmregJumpCCIntegervmregJumpCCNumbervmregLoadAddressvmregLoadDclType
vmregLoadIntegervmregLoadJmpPointervmregLoadNumbervmregLoadTailvmregLoadType
vmregLogNumbervmregMoveImmediatevmregMoveIntegervmregmovenvmregMoveNumber
vmregMulImmediatevmregMulIntegervmregMulNumbervmregNumbervmregObjLength
vmregObjPointervmregOrImmediatevmregOrIntegervmregPwrNumbervmregRefCharacter
vmregRefFloatvmregRefIntegervmregRefLongvmregRefNumbervmregRefShort
vmregRefWordvmregRefXCharactervmregRefXFloatvmregRefXIntegervmregRefXLong
vmregRefXNumbervmregRefXShortvmregRefXWordvmregRunInHarwarevmregSaveDeclType
vmregSaveDeclTypeImmediatevmregSaveIntegervmregSaveNumbervmregSaveTailvmregSaveTailImmediate
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vmregSetXIntImmediatevmregSetXLongvmregSetXLongImmediatevmregSetXNumbervmregSetXShort
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vmregShrIntegervmregSinNumbervmregSqrtNumbervmregStringComparevmregStringiCompare
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vmsetdirkeyvmsetdirvaluevmsetfltvectorvmsetintvectorvmsetlongvector
vmsetmatrixvmsetnummatrixvmsetnumvectorvmsetobjvectorvmsetpcdvector
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vmsubnvmtestescapevmvecBinaryvmvecInitializevmvecLoop
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